1. Field
This disclosure relates to the testing of multi-core processors.
2. Background Information
A Test Access Port (TAP) typically comprises a 4 or 5-pin serial test interface that is compliant with the IEEE 1149.1 specification. IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1 a-1993. It may be used as an access mechanism to implement a boundary scan architecture, as well as other test modes employed to implement the Design For Testability (DFT) methodology on a given integrated circuit (IC). Traditional microprocessor designs have employed a TAP as a mechanism for testing.
A TAP typically has multiple uses. For example, when testing a chip, it is used in a test and manufacturing environment to help debug the chip. As another example, in a system environment, a TAP is used to perform board level interconnect testing between two or more board level components.
As the trend towards higher integration on a given piece of silicon continues, a new class of microprocessors, multi-core microprocessors, have appeared. Traditional microprocessors typically include a block of circuitry which substantially includes the core functions of the processor (hereafter, the “processor core”) and one or more circuit blocks which substantially contain non-core functions, such as, for example, comprising cache, front side bus logic, pads, etc. (hereafter, the “non-processor core” or “non-core”). In contrast, multi-core processors may contain or include a plurality of processor cores and one or more non-processor cores.
Typically, the processor core houses a TAP for the processor. By substantially duplicating the processor core on the integrated circuit (IC), the number of TAPs will, therefore, be increased in this situation. This would potentially increase the number of pins for the IC package. In addition, there may potentially be increases in test time and test vector depth, in order to test each processor core independently. A need, therefore, exists for an improved apparatus or method for implementing an IEEE 1149.1 compliant test access port for a multi-core IC processor.